BCM QS440VA User Manual download pdf (Page 54)

4. BIOS SETUP

Disabled, the writes are not buffered and the CPU must wait until the write is complete

before starting another write cycle.

4.7.5 PCI Dynamic Bursting

When Enabled, every write transaction goes to the write buffer. Burstable transactions

then burst on the PCI bus and nonburstable transactions don’t. The choices: Enabled,

Disabled.

4.7.6 PCI Master 0 WS Write

When Enabled, Writes to the PCI bus are executed with zero wait states. The choices:

Enabled, Disabled.

4.7.7 PCI Delay Transaction

The chipset has an embedded 32-bit posted write buffer to support delay transactions

cycles. Select Enabled to support compliance with PCI specification version 2.1. The

choices: Enabled, Disabled

4.7.8 PCI#2 Access #1 Retry

When PCI#2 (AGP bus) access to PCE#1 (PCI bus) has a error occurred, The choices:

Enabled, Disabled.

4.7.9 AGP Master 1 WS Write

When Enabled, writes to the AGP (Accelerated Graphics Port) are executed with on

wait states.. The choices: Enabled, Disabled.

4.7.10 AGP Master 1 WS Read

When Enabled, read to the AGP (Accelerated Graphics Port) are executed with one

wait states..

4.7.11 PCI IRQ Actived By

This sets the method by which the PCI bus recognizes that an IRQ service is being

requested by a device. Under all circumstances, you should retain the default

configuration unless advised otherwise by your system’s manufacturer. The choices:

Level, Edge.

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BCM QS440VA User Manual Page 54